S9S12XS256J0CAL Datasheet, PDF (290/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC12B16CV1)
10.3.2.10 ATD Input Enable Register (ATDDIEN)
Module Base + 0x000C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IEN[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-13. ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
Table 10-20. ATDDIEN Field Descriptions
Field
Description
15–0
IEN[15:0]
ATD Digital Input Enable on channel x (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls
the digital input buffer from the analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
10.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x000E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CMPHT[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-14. ATD Compare Higher Than Register (ATDCMPHT)
Table 10-21. ATDCMPHT Field Descriptions
Field
Description
15–0
Compare Operation Higher Than Enable for conversion number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5,
CMPHT[15:0] 4, 3, 2, 1, 0) of a Sequence — This bit selects the operator for comparison of conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
S12XS Family Reference Manual, Rev. 1.13
290
Freescale Semiconductor