S9S12XS256J0CAL Datasheet, PDF (277/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Analog-to-Digital Converter (ADC12B16CV1)
Address Name
0x001E
R
ATDDR7
W
0x0020
ATDDR8 ^R
W
0x0022
R
ATDDR9
W
R
0x0024 ATDDR10 _W
R
0x0026 ATDDR11
W
R
0x0028 ATDDR12
W
R
0x002A ATDDR13
W
R
0x002C ATDDR14
W
R
0x002E ATDDR15
W
Bit 7
6
5
4
3
2
1
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
= Unimplemented or Reserved
Figure 10-3. ADC12B16C Register Summary (Sheet 2 of 2)
Bit 0
10.3.2 Register Descriptions
This section describes in address order all the ADC12B16C registers and their individual bits.
10.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Module Base + 0x0000
R
W
Reset
7
Reserved
0
Read: Anytime
6
5
4
3
2
0
0
0
WRAP3
WRAP2
0
0
0
1
1
= Unimplemented or Reserved
Figure 10-4. ATD Control Register 0 (ATDCTL0)
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Table 10-2. ATDCTL0 Field Descriptions
Field
Description
1
WRAP1
1
0
WRAP0
1
3-0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
WRAP[3-0] multi-channel conversions. The coding is summarized in Table 10-3.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
277