S9S12XS256J0CAL Datasheet, PDF (125/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Port P pins PP[7:3] can be used for either general purpose I/O with pin interrupt capability, or with the
PWM or with the channels of the standard Timer.subsystem.
Port P pins PP[2,0] can be used for either general purpose I/O, or with the PWM or with the TIM or with
the SCI1 subsystem.
Port P pin PP[1] can be used for either general purpose I/O, or with the PWM or with the TIM subsystem.
2.4.3.9 Port H
Port H pins PH[7:0] can be used for general purpose I/O with pin interrupt capability.
2.4.3.10 Port J
Port J pins PJ[7,6,1,0] can be used for general purpose I/O with pin-interrupt capability.
2.4.3.11 Port AD
This port is associated with the ATD.
Port AD pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.4 Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on a per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 2-75) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-74 and
Table 2-72).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t_pign
t_pval
Figure 2-74. Interrupt Glitch Filter on Port P, H and J (PPS=0)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
125