S9S12XS256J0CAL Datasheet, PDF (694/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Characteristics
A.8 SPI Timing
This section provides electrical parametrics and ratings for the SPI. In Table A-26 the measurement
conditions are listed.
Table A-26. Measurement Conditions
Description
Value
Unit
Drive mode
Full drive mode
—
Load capacitance C_LOAD1, on all outputs
50
pF
Thresholds for delay measurement points
(20% / 80%) V_DDX
V
1 ^{Timing specified for equal load on all SPI output pins. Avoid asymmetric load.}
A.8.1 Master Mode
In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
SS
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
2
1
12
4
4
12
5
6
MSB IN2
10
MSB OUT2
Bit MSB-1. . . 1
9
Bit MSB-1. . . 1
13
13
LSB IN
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
Figure A-6. SPI Master Timing (CPHA = 0)
3
11
S12XS Family Reference Manual, Rev. 1.13
694
Freescale Semiconductor