S9S12XS256J0CAL Datasheet, PDF(53/738 Page) Freescale Semiconductor, Inc – Microcontrollers

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S9S12XS256J0CAL Datasheet, PDF (53/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Device Overview S12XS Family

Table 1-10. Interrupt Vector Locations (Sheet 2 of 2)

Vector Address1

Vector base + $BA

Vector base + $B8

Vector base + $B6

Vector base + $B4

Interrupt Source

FLASH Fault Detect

FLASH

CAN0 wake-up

CAN0 errors

Vector base + $B2

CAN0 receive

Vector base + $B0

CAN0 transmit

Vector base + $AE

to

Vector base + $90

Vector base + $8E

Port P Interrupt

Vector base+ $8C

PWM emergency shutdown

Vector base + $8A

to

Vector base + $82

Vector base + $80

Low-voltage interrupt (LVI)

Vector base + $7E Autonomous periodical interrupt (API)

Vector base + $7C

High Temperature Interrupt (HTI)

Vector base + $7A

Periodic interrupt timer channel 0

Vector base + $78

Periodic interrupt timer channel 1

Vector base + $76

Periodic interrupt timer channel 2

Vector base + $74

Periodic interrupt timer channel 3

Vector base + $72

to

Vector base + $40

Vector base + $3E

ATD0 Compare Interrupt

Vector base + $3C

to

Vector base + $14

Vector base + $12

System Call Interrupt (SYS)

Vector base + $10

1 16 bits vector address based

Spurious interrupt

CCR

Mask

Local Enable

STOP WAIT

Wake up Wake up

I bit FCNFG2 (SFDIE, DFDIE) No

No

I bit

FCNFG (CCIE)

No

Yes

I bit

CAN0RIER (WUPIE)

Yes

Yes

I bit

CAN0RIER (CSCIE,

OVRIE)

No

Yes

I bit

CAN0RIER (RXFIE)

No

Yes

I bit CAN0TIER (TXEIE[2:0])

No

Yes

Reserved

I bit

PIEP (PIEP7-PIEP0)

I bit

PWMSDN (PWMIE)

Yes

Yes

No

Yes

Reserved

I bit

VREGCTRL (LVIE)

No

Yes

I bit VREGAPICTRL (APIE)

Yes

Yes

I bit

VREGHTCL (HTIE)

No

Yes

I bit

PITINTE (PINTE0)

No

Yes

I bit

PITINTE (PINTE1)

No

Yes

I bit

PITINTE (PINTE2)

No

Yes

I bit

PITINTE (PINTE3)

No

Yes

Reserved

I bit

ATD0CTL2 (ACMPIE)

Yes

Yes

Reserved

â

None

â

None

â

â

â

â

1.6.3 Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections

for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers.

S12XS Family Reference Manual, Rev. 1.13

Freescale Semiconductor

53

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