S9S12XS256J0CAL Datasheet, PDF (89/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Table 2-21. PPST Register Field Descriptions
Field
7-0
PPST
Description
Port T pull device select—Configure pull device polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device selected
0 A pull-up device selected
2.3.24 PIM Reserved Register
Address 0x0246
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-22. PIM Reserved Register
Access: User read¹
1
0
0
0
0
0
2.3.25 Port T Routing Register (PTTRR)
Address 0x0247
R
W
Routing
Option
Reset
7
PTTRR7
PWM7
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
PTTRR6
PTTRR5
PTTRR4
PTTRR2
PWM6
PWM5
PWM4
—
IOC2
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-23. Port T Routing Register (PTTRR)
Access: User read¹
1
0
PTTRR1
PTTRR0
IOC1
0
IOC0
0
This register configures the re-routing of PWM and TIM channels on alternative pins.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
89