S9S12XS256J0CAL Datasheet, PDF (82/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
Table 2-12. ECLKCTL Register Field Descriptions
Field
Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
6
No ECLKX2—Disable ECLKX2 output
NCLKX2 This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
5
DIV16
1 ECLKX2 disabled
0 ECLKX2 enabled
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
4-0
EDIV
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3
...
11111 ECLK rate = bus clock rate divided by 32
2.3.13 PIM Reserved Register
Address 0x001D (PRR)
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-11. PIM Reserved Register
Access: User read¹
1
0
0
0
0
0
S12XS Family Reference Manual, Rev. 1.13
82
Freescale Semiconductor