S9S12XS256J0CAL Datasheet, PDF (132/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Mapping Control (S12XMMCV4)
3.3.2.1 Mode Register (MODE)
Address: 0x000B PRR
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
MODC
W
Reset MODC¹
0
0
0
0
0
0
0
1. External signal (see Table 3-2).
= Unimplemented or Reserved
Figure 3-3. Mode Register (MODE)
Read: Anytime. Write: Only if a transition is allowed (see Figure 3-5).
The MODE bits of the MODE register are used to establish the MCU operating mode.
Field
7
MODC
Table 3-3. MODE Field Descriptions
Description
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external
mode pin MODC determines the operating mode during RESET low (active). The state of the pin is latched into
the respective register bit after the RESET signal goes inactive (see Figure 3-3).
Write restrictions exist to disallow transitions between certain modes. Figure 3-5 illustrates all allowed mode
changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to
these register bits except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
Figure 3-4.
Normal
1
RESET
Single-Chip
1
(NS)
1
Transition done by external pins (MODC)
RESET
State
Transition done by write access to the MODE register
State
State
Special
Single-Chip
(SS)
0
0
RESET
Figure 3-5. Mode Transition Diagram when MCU is Unsecured
S12XS Family Reference Manual, Rev. 1.13
132
Freescale Semiconductor