S9S12XS256J0CAL Datasheet, PDF (120/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port Integration Module (S12XSPIMV1)
2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0)
Address 0x0277
Access: User read/write¹
7
R
PER1AD07
W
6
PER1AD06
5
PER1AD05
4
PER1AD04
3
PER1AD03
2
PER1AD02
1
PER1AD01
0
PER1AD00
Reset
0
0
0
0
0
0
0
0
1 _{Read: Anytime}
Write: Anytime
Figure 2-71. Port AD0 Pull Up Enable Register 1 (PER1AD0)
Table 2-70. PER1AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 pull device enable—Enable pull-up device on input pin
PER1AD0 This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
2.3.74 PIM Reserved Registers
Address 0x0278-0x27F
7
6
5
4
3
2
R
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
1 _{Read: Always reads 0x00}
Write: Unimplemented
Figure 2-72. PIM Reserved Registers
2.4 Functional Description
Access: User read¹
1
0
0
0
0
0
2.4.1 General
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output or input of a peripheral module.
S12XS Family Reference Manual, Rev. 1.13
120
Freescale Semiconductor