S9S12XS256J0CAL Datasheet, PDF (354/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Periodic Interrupt Timer (S12PIT24B4CV1)
12.3.0.2 PIT Force Load Timer Register (PITFLT)
Module Base + 0x0001
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
0
0
0
0
0
PFLT3
PFLT2
0
0
0
0
0
Figure 12-4. PIT Force Load Timer Register (PITFLT)
1
0
PFLT1
0
Table 12-3. PITFLT Field Descriptions
0
0
PFLT0
0
Field
Description
3:0
PFLT[3:0]
PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
12.3.0.3 PIT Channel Enable Register (PITCE)
Module Base + 0x0002
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
0
0
0
PCE3
PCE2
0
0
0
0
0
Figure 12-5. PIT Channel Enable Register (PITCE)
Table 12-4. PITCE Field Descriptions
1
PCE1
0
0
PCE0
0
Field
Description
3:0
PCE[3:0]
PIT Enable Bits for Timer Channel 3:0 — These bits enable the PIT channels 3-0. If PCE is cleared, the PIT
channel is disabled and the corresponding flag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
S12XS Family Reference Manual, Rev. 1.13
354
Freescale Semiconductor