S9S12XS256J0CAL Datasheet, PDF (101/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.40 Port M Wired-Or Mode Register (WOMM)
Port Integration Module (S12XSPIMV1)
Address 0x0256
R
W
Reset
7
WOMM7
0
1 _{Read: Anytime}
Write: Anytime
6
WOMM6
5
WOMM5
4
WOMM4
3
WOMM3
2
WOMM2
0
0
0
0
0
Figure 2-38. Port M Wired-Or Mode Register (WOMM)
Access: User read/write¹
1
0
WOMM1 WOMM0
0
0
Table 2-36. WOMM Register Field Descriptions
Field
Description
7-0
WOMM
Port M wired-or mode—Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins.
In wired-or mode a logic “0” is driven active low while a logic “1” remains undriven. This allows a multipoint
connection of several serial modules. The bit has no influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
2.3.41 Module Routing Register (MODRR)
Address 0x0257
7
6
5
4
3
2
R
0
0
0
MODRR7 MODRR6
MODRR4
W
Routing
Option
SCI1
SCI1
—
SPI0
—
—
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{Read: Anytime}
Write: Anytime
Figure 2-39. Module Routing Register (MODRR)
This register configures the re-routing of SCI1 and SPI0 on alternative ports.
Access: User read/write¹
1
0
0
0
—
—
0
0
MODRRx
76
Table 2-37. SCI1 Routing
TXD
Related Pins
RXD
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
101