S9S12XS256J0CAL Datasheet, PDF (516/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

256 KByte Flash Module (S12XFTMR256K1V1)
Address
& Name
7
6
5
4
3
2
1
0
0x0010
R NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
FOPT
W
0x0011
R
0
0
0
0
0
0
0
0
FRSV2 _W
0x0012
R
0
0
0
0
0
0
0
0
FRSV3 _W
0x0013
R
0
0
0
0
0
0
0
0
FRSV4 _W
= Unimplemented or Reserved
Figure 18-4. FTMR256K1 Register Summary (continued)
18.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIV[6:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Table 18-6. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6–0
FDIV[6:0]
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms. Table 18-7 shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to Section 18.4.1, “Flash Command Operations,” for more information.
S12XS Family Reference Manual, Rev. 1.13
516
Freescale Semiconductor