S9S12XS256J0CAL Datasheet, PDF(505/738 Page) Freescale Semiconductor, Inc – Microcontrollers

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S9S12XS256J0CAL Datasheet, PDF (505/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Voltage Regulator (S12VREGL3V3V1)

17.4.11.1 Low-Voltage Interrupt (LVI)

In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the

status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An

interrupt, indicated by ï¬ag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable

bit LVIE = 1.

NOTE

On entering the Reduced Power Mode, the LVIF is not cleared by the

VREG_3V3.

17.4.11.2 HTI - High Temperature Interrupt

In FPM VREG monitors the die temperature TDIE. Whenever TDIE exceeds level THTIA the status bit

HTDS is set to 1. Vice versa, HTDS is reset to 0 when TDIE get below level THTID. An interrupt, indicated

by ï¬ag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.

NOTE

On entering the Reduced Power Mode the HTIF is not cleared by the VREG.

17.4.11.3 Autonomous Periodical Interrupt (API)

As soon as the conï¬gured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated

by ï¬ag APIF = 1, is triggered if interrupt enable bit APIE = 1.

S12XS Family Reference Manual, Rev. 1.13

Freescale Semiconductor

505

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