S9S12XS256J0CAL Datasheet, PDF (673/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

A.2 ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
Electrical Characteristics
A.2.1 ATD Operating Characteristics
The Table A-14 and Table A-15 show conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V_SSA ≤ V_RL ≤ V_IN ≤ V_RH ≤ V_DDA.
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-14. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 3.13 V < V_DDA < 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 D Reference potential
Low
High
V_RL
V_SSA
—
V_DDA/2
V
V_RH
V_DDA/2
—
V_DDA
V
2 D Voltage difference V_DDX to V_DDA
∆_VDDX
–2.35
0
0.1
V
3 D Voltage difference V_SSX to V_SSA
4 C Differential reference voltage¹
∆_VSSX
–0.1
0
V_RH-V_RL
3.13
5.0
0.1
V
5.5
V
5 C ATD Clock Frequency (derived from bus clock via the
0.25
—
prescaler bus)
f_ATDCLk
8.3
MHz
6 P ATD Clock Frequency in Stop mode (internal generated
temperature and voltage dependent clock, ICLK)
0.6
1
1.7
MHz
7 D ADC conversion in stop, recovery time²
t_ATDSTPRCV
—
—
1.5
µs
ATD Conversion Period³
8 D ^{12 bit resolution:}
10 bit resolution:
8 bit resolution:
N_CONV12
20
—
42
ATD
N_CONV10
19
—
41
clock
N_CONV8
17
—
39
cycles
1 ^{Full accuracy is not guaranteed when differential voltage is less than 4.50 V}
2 ^{When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock}
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
3 ^{The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock}
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
A.2.2 Factors Influencing Accuracy
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.2.2.1 Port AD Output Drivers Switching
PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
673