S9S12XS256J0CAL Datasheet, PDF (107/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.47 Port P Polarity Select Register (PPSP)
Port Integration Module (S12XSPIMV1)
Address 0x025D
R
W
Reset
7
PPSP7
0
1 _{Read: Anytime}
Write: Anytime
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
0
0
0
0
0
Figure 2-45. Port P Polarity Select Register (PPSP)
Access: User read/write¹
1
0
PPSP1
PPSP0
0
0
Table 2-44. PPSP Register Field Descriptions
Field
7-0
PPSP
Description
Port P pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
2.3.48 Port P Interrupt Enable Register (PIEP)
Address 0x025E
R
W
Reset
7
PIEP7
0
1 _{Read: Anytime}
Write: Anytime
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
0
0
0
0
0
Figure 2-46. Port P Interrupt Enable Register (PIEP)
Access: User read/write¹
1
0
PIEP1
PIEP0
0
0
Field
7-0
PIEP
Table 2-45. PIEP Register Field Descriptions
Description
Port P interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
107