S9S12XS256J0CAL Datasheet, PDF (708/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

PCB Layout Guidelines
Appendix C
PCB Layout Guidelines
C.1 General
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
• Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins .
• Central point of the ground star should be the VSS3 pin.
• Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.
• VSSPLL must be directly connected to VSS3.
• Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for C7,
C8, and Q1 as small as possible.
• Do not place other signals or supplies underneath area occupied by C7, C8, and Q1 and the
connection area to the MCU.
• Central power input should be fed in at the VDDA/VSSA pins.
Example layouts are illustrated on the following pages.
Table C-1. Recommended Decoupling Capacitor Choice
Component
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Q1
Purpose
V_DDF filter capacitor
N/A
V_DDX2 filter capacitor
V_DDPLL filter capacitor
OSC load capacitor
OSC load capacitor
V_DDR filter capacitor
N/A
V_DD filter capacitor
V_DDA1 filter capacitor
V_DDX1 filter capacitor
Quartz
Type
Value
Ceramic X7R
—
220 nF
—
X7R/tantalum
>=100 nF
Ceramic X7R
220 nF
From crystal manufacturer
X7R/tantalum
—
Ceramic X7R
Ceramic X7R
X7R/tantalum
—
>=100 nF
—
220 nF
>=100 nF
>=100 nF
—
S12XS Family Reference Manual, Rev. 1.13
708
Freescale Semiconductor