S9S12XS256J0CAL Datasheet, PDF (115/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.63 Port J Polarity Select Register (PPSJ)
Port Integration Module (S12XSPIMV1)
Address 0x026D
R
W
Reset
7
PPSJ7
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
PPSJ6
0
0
0
0
0
Figure 2-61. Port J Polarity Select Register (PPSJ)
Access: User read/write¹
1
0
PPSJ1
PPSJ0
0
0
Table 2-60. PPSJ Register Field Descriptions
Field
Description
7-6, 1-0
PPSJ
Port J pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
2.3.64 Port J Interrupt Enable Register (PIEJ)
Address 0x026E
R
W
Reset
7
PIEJ7
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
PIEJ6
0
0
0
0
0
Figure 2-62. Port J Interrupt Enable Register (PIEJ)
Access: User read/write¹
1
0
PIEJ1
PIEJ0
0
0
Table 2-61. PIEJ Register Field Descriptions
Field
Description
7-6, 1-0 Port J interrupt enable—
PIEJ This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
115