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S9S12XS256J0CAL Datasheet, PDF (20/738 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Device Overview S12XS Family
⢠INT (interrupt module)
â Seven levels of nested interrupts
â Flexible assignment of interrupt sources to each interrupt level.
â External non-maskable high priority interrupt (XIRQ)
â The following inputs can act as Wake-up Interrupts
â IRQ and non-maskable XIRQ
â CAN receive pins
â SCI receive pins
â Depending on the package option up to 20 pins on ports J, H and P conï¬gurable as rising or
falling edge sensitive
⢠MMC (module mapping control)
⢠DBG (debug module)
â Monitoring of CPU bus with tag-type or force-type breakpoint requests
â 64 x 64-bit circular trace buffer captures change-of-ï¬ow or memory access information
⢠BDM (background debug mode)
⢠OSC_LCP (oscillator)
â Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
â Good noise immunity
â Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
â Transconductance sized for optimum start-up margin for typical crystals
⢠IPLL (Internally ï¬ltered, frequency modulated phase-locked-loop clock generation)
â No external components required
â Conï¬gurable option to spread spectrum for reduced EMC radiation (frequency modulation)
⢠CRG (clock and reset generation)
â COP watchdog
â Real time interrupt
â Clock monitor
â Fast wake up from STOP in self clock mode
⢠Memory Options
â 64, 128 and 256 Kbyte Flash
â Flash General Features
â 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure
correction and double fault detection
â Erase sector size 1024 bytes
â Automated program and erase algorithm
â Protection scheme to prevent accidental program or erase
â Security option to prevent unauthorized access
â Sense-amp margin level setting for reads
â 4 and 8 Kbyte Data Flash space
S12XS Family Reference Manual, Rev. 1.13
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Freescale Semiconductor
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