S9S12XS256J0CAL Datasheet, PDF (692/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Characteristics
For N < 1000, the following equation is a good fit for the maximum jitter:
J(N)
=
---^j--¹---
N
+
j₂
J(N)
1
5
10
20
N
Figure A-5. Maximum bus clock jitter approximation
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter
to a large extent.
Table A-24. IPLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 P _{Self Clock Mode frequency}¹
f_SCM
1
—
4
MHz
2 T VCO locking range
f_VCO
32
—
120
MHz
3 T Reference Clock
f_REF
1
—
40
MHz
4 D Lock Detection
|∆_Lock|
0
—
1.5
%²
5 D Un-Lock Detection
|∆_unl|
0.5
—
2.5
%²
7 C Time to lock
t_lock
—
150 +
214
256/f_REF
µs
8 C _{Jitter fit parameter 1}³
j₁
—
—
1.2
%
9 C _{Jitter fit parameter 2}³
j₂
—
—
0
%
10 C Bus Frequency for FM1=1, FM0=1 (frequency
modulation in PLLCTL register of s12xe_crg)
f_bus
—
—
38
MHz
11 C Bus Frequency for FM1=1, FM0=0 (frequency
modulation in PLLCTL register of s12xe_crg)
f_bus
—
—
39
MHz
12 C Bus Frequency for FM1=0, FM0=1 (frequency
modulation in PLLCTL register of s12xe_crg)
f_bus
—
—
39
MHz
1 ^{Bus frequency is equivalent to f}SCM^/2
2 ^{% deviation from target frequency}
3 ^fOSC^{=4MHz, f}BUS^{=40MHz equivalent f}PLL^{=80MHz: REFDIV=$00, REFRQ=01, SYNDIV=$09, VCOFRQ=01, POSTDIV=$00}
S12XS Family Reference Manual, Rev. 1.13
692
Freescale Semiconductor