S9S12XS256J0CAL Datasheet, PDF (321/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 11-26. Message Buffer Organization
Offset
Address
Register
0x00X0 Identifier Register 0
0x00X1 Identifier Register 1
0x00X2 Identifier Register 2
0x00X3 Identifier Register 3
0x00X4 Data Segment Register 0
0x00X5 Data Segment Register 1
0x00X6 Data Segment Register 2
0x00X7 Data Segment Register 3
0x00X8 Data Segment Register 4
0x00X9 Data Segment Register 5
0x00XA Data Segment Register 6
0x00XB Data Segment Register 7
0x00XC
0x00XD
Data Length Register
Transmit Buffer Priority Register⁽¹⁾
0x00XE Time Stamp Register (High Byte)
0x00XF Time Stamp Register (Low Byte)
1. Not applicable for receive buffers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Figure 11-24 shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 11-25.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation¹.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
1. Exception: The transmit buffer priority registers are 0 out of reset.
S12XS Family Reference Manual Rev. 1.13
Freescale Semiconductor
321