S9S12XS256J0CAL Datasheet, PDF (49/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device Overview S12XS Family
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-6, these system clocks are used throughout the MCU to drive the core,
the memories, and the peripherals.
The program Flash memory is supplied by the bus clock and the oscillator clock. The oscillator clock is
used as a time base to derive the program and erase times for the NVMs.
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the oscillator clock. This allows the user to select its clock based on the required jitter
performance.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the
output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
1.4 Modes of Operation
The MCU can operate in different modes. These are described in 1.4.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.4.2 Power Modes.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging. This is described in 1.4.3 Freeze Mode.
1.4.1 Chip Configuration Summary
The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-
8). The MODC bit in the MODE register shows the current operating mode and provides limited mode
switching during operation. The state of the MODC signal is latched into this bit on the rising edge of
RESET.
Table 1-8. Chip Modes
Chip Modes
Normal single chip
Special single chip
MODC
1
0
1.4.1.1 Normal Single-Chip Mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
49