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S9S12XS256J0CAL Datasheet, PDF (202/738 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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S12X Debug (S12XDBGV3) Module
Table 6-7. SSF[2:0] â State Sequence Flag Bit Encoding
SSF[2:0]
000
001
010
011
100
101,110,111
Current State
State0 (disarmed)
State1
State2
State3
Final State
Reserved
6.3.2.3 Debug Trace Control Register (DBGTCR)
Address: 0x0022
R
W
Reset
7
reserved
0
6
TSOURCE
5
4
TRANGE
3
2
TRCMOD
0
0
0
0
0
Figure 6-5. Debug Trace Control Register (DBGTCR)
1
0
TALIGN
0
0
Read: Anytime
Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Bits 5:0 anytime the module is disarmed.
WARNING
DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus
preventing proper operation.
Table 6-8. DBGTCR Field Descriptions
Field
Description
6
TSOURCE
Trace Source Control Bits â The TSOURCE enables the tracing session. If the MCU system is secured, this
bit cannot be set and tracing is inhibited.
0 No tracing selected
1 Tracing selected
5â4
TRANGE
Trace Range Bits â The TRANGE bits allow ï¬ltering of trace information from a selected address range when
tracing from the CPU12X in Detail Mode. To use a comparator for range ï¬ltering, the corresponding COMPE
bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state
sequence triggers. See Table 6-9.
3â2
TRCMOD
Trace Mode Bits â See Section 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of ï¬ow
information is stored. In Loop1 Mode, change of ï¬ow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
Table 6-10.
1â0
Trigger Align Bits â These bits control whether the trigger is aligned to the beginning, end or the middle of a
TALIGN tracing session. See Table 6-11.
S12XS Family Reference Manual, Rev. 1.13
202
Freescale Semiconductor
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