S9S12XS256J0CAL Datasheet, PDF (212/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

S12X Debug (S12XDBGV3) Module
Table 6-27. DBGXCTL Field Descriptions (continued)
Field
0
COMPE
Description
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
Table 6-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
Table 6-28. Read or Write Comparison Logic Table
RWE Bit
0
0
1
1
1
1
RW Bit
x
x
0
0
1
1
RW Signal
0
1
0
1
0
1
Comment
RW not used in comparison
RW not used in comparison
Write
No match
No match
Read
6.3.2.8.2 Debug Comparator Address High Register (DBGXAH)
Address: 0x0029
7
R
0
W
6
Bit 22
5
Bit 21
4
Bit 20
Reset
0
0
0
0
= Unimplemented or Reserved
3
Bit 19
0
2
Bit 18
0
1
Bit 17
0
Figure 6-15. Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
0
Bit 16
0
Table 6-29. DBGXAH Field Descriptions
Field
Description
6–0
Bit[22:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. .
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
S12XS Family Reference Manual, Rev. 1.13
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Freescale Semiconductor