S9S12XS256J0CAL Datasheet, PDF (21/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device Overview S12XS Family
– 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure
correction and double fault detection
– Erase sector size 256 bytes
– Automated program and erase algorithm
— 4, 8 and 12 Kbyte RAM
• 16-channel, 12-bit Analog-to-Digital converter
— 8/10/12 Bit resolution
— 3µs, 10-bit single conversion time
— Left or right justified result data
— External and internal conversion trigger capability
— Internal oscillator for conversion in Stop modes
— Wake from low power modes on analog comparison > or <= match
— Continuous conversion mode
— Multiplexer for 16 analog input channels
— Multiple channel scans
— Pins can also be used as digital I/O
• MSCAN (1 M bit per second, CAN 2.0 A, B software compatible module)
— 1 Mbit per second, CAN 2.0 A, B software compatible module
– Standard and extended data frames
– 0 - 8 bytes data length
– Programmable bit rate up to 1 Mbps
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization
— Flexible identifier acceptance filter programmable as:
– 2 x 32-bit
– 4 x 16-bit
– 8 x 8-bit
— Wake-up with integrated low pass filter option
— Loop back for self test
— Listen-only mode to monitor CAN bus
— Bus-off recovery by software intervention or automatically
— 16-bit time stamp of transmitted/received messages
• TIM (standard timer module)
— 8 x 16-bit channels for input capture or output compare
— 16-bit free-running counter with 8-bit precision prescaler
— 1 x 16-bit pulse accumulator
• PIT (periodic interrupt timer)
— Up to four timers with independent time-out periods
— Time-out periods selectable between 1 and 2²⁴ bus clock cycles
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
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