S9S12XS256J0CAL Datasheet, PDF (490/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

Voltage Regulator (S12VREGL3V3V1)
3. Shutdown mode
Controlled by VREGEN (see device level specification for connectivity of VREGEN).
This mode is characterized by minimum power consumption. The regulator outputs are in a high-
impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API
internal RC oscillator clock is not available.
This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the
VREG_3V3 to use external supplies.
17.1.3 Block Diagram
Figure 17-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output
voltages.
S12XS Family Reference Manual, Rev. 1.13
490
Freescale Semiconductor