S9S12XS256J0CAL Datasheet, PDF (633/738 Pages) Freescale Semiconductor, Inc – Microcontrollers

64 KByte Flash Module (S12XFTMR64K1V1)
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
ECCR[15:8]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
ECCR[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-21. Flash ECC Error Results Low Register (FECCRLO)
All FECCR bits are readable but not writable.
Table 20-25. FECCR Index Settings
ECCRIX[2:0]
FECCR Register Content
Bits [15:8]
Bit[7]
Bits[6:0]
000
Parity bits read from
Flash block
0
Global address
[22:16]
001
Global address [15:0]
010
Data 0 [15:0]
011
Data 1 [15:0] (P-Flash only)
100
Data 2 [15:0] (P-Flash only)
101
Data 3 [15:0] (P-Flash only)
110
Not used, returns 0x0000 when read
111
Not used, returns 0x0000 when read
Table 20-26. FECCR Index=000 Bit Descriptions
Field
Description
15:8
PAR[7:0]
ECC Parity Bits — Contains the 8 parity bits from the 72 bit wide P-Flash data word or the 6 parity bits,
allocated to PAR[5:0], from the 22 bit wide D-Flash word with PAR[7:6]=00.
6–0
Global Address — The GADDR[22:16] field contains the upper seven bits of the global address having
GADDR[22:16] caused the error.
S12XS Family Reference Manual, Rev. 1.13
Freescale Semiconductor
633