S912XEG128J2MAA Datasheet, PDF (92/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Port Pin Name
E
PE[7]
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]
PE[1]
PE[0]
K
PK[7]
PK[6:4]
PK[3:0]
Pin Function
& Priority⁽¹⁾
XCLKS ²
ECLKX2
GPIO
MODB ²
TAGHI
GPIO
MODA ²
RE
TAGLO
GPIO
ECLK
GPIO
EROMCTL ²
LSTRB
LDS
GPIO
RW
WE
GPIO
IRQ
GPI
XIRQ
GPI
ROMCTL ²
EWAIT
GPIO
ADDR[22:20]
mux
ACC[2:0] ³
GPIO
ADDR[19:16]
mux
IQSTAT[3:0] ³
GPIO
I/O
Description
Pin Function
after Reset
I External clock selection input during RESET
I Free-running clock output at Core Clock rate (ECLK x 2)
I/O General-purpose I/O
I MODB input during RESET
I Instruction tagging low pin
Configurable for reduced input threshold
I/O General-purpose I/O
I MODA input during RESET
O Read enable signal
I Instruction tagging low pin
Configurable for reduced input threshold
I/O General-purpose I/O
O Free-running clock output at the Bus Clock rate or programmable
divided in normal modes
I/O General-purpose I/O
I EROMON bit control input during RESET
O Low strobe bar output
O Lower data strobe
I/O General-purpose I/O
O Read/write output for external bus
O Write enable signal
I/O General-purpose I/O
I Maskable level- or falling edge-sensitive interrupt input
I General-purpose input
I Non-maskable level-sensitive interrupt input
I General-purpose input
I ROMON bit control input during RESET
I External Wait signal
Configurable for reduced input threshold
I/O General-purpose I/O
O Extended external bus address output
(multiplexed with access master output)
Mode
dependent ⁴
Mode
dependent ³
I/O General-purpose I/O
O Extended external bus address output
(multiplexed with instruction pipe status bits)
I/O General-purpose I/O
MC9S12XE-Family Reference Manual Rev. 1.25
92
Freescale Semiconductor