S912XEG128J2MAA Datasheet, PDF (165/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.87
Chapter 2 Port Integration Module (S12XEPIMV1)
Port R Data Direction Register (DDRR)
Address 0x036A
R
W
Reset
7
DDRR7
0
1. Read: Anytime.
Write: Anytime.
6
DDRR6
5
DDRR5
4
DDRR4
3
DDRR3
2
DDRR2
0
0
0
0
0
Figure 2-85. Port R Data Direction Register (DDRR)
Access: User read/write⁽¹⁾
1
0
DDRR1
DDRR0
0
0
Table 2-83. DDRR Register Field Descriptions
Field
7-0
DDRR
Description
Port R data direction—
This register controls the data direction of pins 7 through 0.
The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
2.3.88 Port R Reduced Drive Register (RDRR)
Address 0x036B
R
W
Reset
7
RDRR7
0
1. Read: Anytime.
Write: Anytime.
6
RDRR6
5
RDRR5
4
RDRR4
3
RDRR3
2
RDRR2
0
0
0
0
0
Figure 2-86. Port R Reduced Drive Register (RDRR)
Access: User read/write⁽¹⁾
1
0
RDRR1
RDRR0
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
165