S912XEG128J2MAA Datasheet, PDF (469/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1)
Table 11-1. Revision History
Revision
Number
V01.03
V01.04
V01.05
V01.06
Revision
Date
1 Sep. 2008
20 Nov. 2008
19. Sep 2009
18. Sep 2012
Sections
Affected
Description of Changes
Table 11-14 added 100MHz example for PLL
11.3.2.4/11-475 S12XECRG Flags Register: corrected address to Module Base + 0x0003
11.5.1/11-495 Modified Note below Table 11-17./11-495
Table 11-14
11.5.1
Added footnote concerning maximum clock frequencies to table
Removed redundant examples from table
Replaced reference to MMC documentation
11.1 Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
11.1.1 Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
• System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
• Computer Operating Properly (COP) watchdog timer with time-out clear window.
• System Reset generation from the following possible sources:
— Power on reset
— Low voltage reset
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
469