S912XEG128J2MAA Datasheet, PDF (254/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 External Bus Interface (S12XEBIV4)
Read data are not captured in emulation expanded mode until the specified setup time before the falling
edge of ECLK.
In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by
EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is
not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched
as programmed and controlled by external wait.
5.4.5 Data Select and Data Direction Signals
The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of
the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses.
The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this
module exclusively supports these kind of accesses in a single cycle.
With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus
halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to
odd addresses.
In expanded modes the data access type is externally determined by a set of control signals, i.e., data select
and data direction signals, as described below. The data select signals are not available if using the external
bus interface with an 8-bit data bus.
5.4.5.1 Normal Expanded Mode
In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write),
data size and alignment of an external bus access (Table 5-19).
Table 5-19. Access in Normal Expanded Mode
Access
DATA[15:8]
DATA[7:0]
RE WE UDS LDS
I/O data(addr) I/O data(addr)
Word write of data on DATA[15:0] at an even and even+1 address 1 0 0
Byte write of data on DATA[7:0] at an odd address
10 1
0 Out data(even) Out data(odd)
0 In
x
Out data(odd)
Byte write of data on DATA[15:8] at an even address
10 0
Word read of data on DATA[15:0] at an even and even+1 address 0 1 0
Byte read of data on DATA[7:0] at an odd address
01 1
Byte read of data on DATA[15:8] at an even address
01 0
Indicates No Access
11 1
Unimplemented
11 1
11 0
1 Out data(even) In
x
0 In data(even) In data(odd)
0 In
x
In data(odd)
1 In data(even) In
x
1 In
x
In
x
0 In
x
In
x
1 In
x
In
x
5.4.5.2 Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
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