S912XEG128J2MAA Datasheet, PDF(379/1324 Page) Freescale Semiconductor, Inc – Microcontrollers

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S912XEG128J2MAA Datasheet, PDF (379/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

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10.5 Interrupts

Chapter 10 XGATE (S12XGATEV3)

10.5.1 Incoming Interrupt Requests

XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see

S12X_INT Section). Only a subset of the MCUâs interrupt requests can be routed to the XGATE. Which

speciï¬c interrupt requests these are and which channel ID they are assigned to is documented in Section

âInterruptsâ of the device overview.

10.5.2 Outgoing Interrupt Requests

There are three types of interrupt requests which can be triggered by the XGATE module:

4. Channel interrupts

For each XGATE channel there is an associated interrupt ï¬ag in the XGATE interrupt ï¬ag vector

(XGIF, see Section 10.3.1.8, âXGATE Channel Interrupt Flag Vector (XGIF)â). These ï¬ags can be

set through the "SIF" instruction by the RISC core. They are typically used to ï¬ag an interrupt to

the S12X_CPU when the XGATE has completed one of its task.

5. Software triggers

Software triggers are interrupt ï¬ags, which can be set and cleared by software (see

Section 10.3.1.9, âXGATE Software Trigger Register (XGSWT)â). They are typically used to

trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to

the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software.

6. Software error interrupt

The software error interrupt signals to the S12X_CPU the detection of an error condition in the

XGATE application code (see Section 10.4.5, âSoftware Error Detectionâ). This is a non-maskable

interrupt. Executing the interrupt service routine will automatically reset the interrupt line.

All outgoing XGATE interrupts, except software error interrupts, can be disabled by the XGIE bit in the

XGATE module control register (XGMCTL, see Section 10.3.1.1, âXGATE Control Register

(XGMCTL)â).

10.6 Debug Mode

The XGATE debug mode is a feature to allow debugging of application code.

10.6.1 Debug Features

In debug mode the RISC core will be halted and the following debug features will be enabled:

â¢ Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1âXGR7)1

All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue

program execution with the modified register values.

1. Only possible if MCU is unsecured

MC9S12XE-Family Reference Manual Rev. 1.25

Freescale Semiconductor

379

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