S912XEG128J2MAA Datasheet, PDF (472/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12XECRG.
11.3.1 Module Memory Map
Figure 11-2 gives an overview on all S12XECRG registers.
Address Name
Bit 7
6
5
4
0x0000
R
SYNR
W
VCOFRQ[1:0]
R
0x0001 REFDV
W
REFFRQ[1:0]
R
0
0
0
0x0002 POSTDIV
W
R
0x0003 CRGFLG
W
RTIF
PORF
LVRF LOCKIF
R
0
0x0004 CRGINT
RTIE
W
0
LOCKIE
R
XCLKS
0
0x0005 CLKSEL
PLLSEL PSTP
W
R
0x0006 PLLCTL
W
CME
PLLON
FM1
FM0
R
0x0007 RTICTL
RTDEC
W
RTR6
RTR5
RTR4
R
0
0
0x0008 COPCTL
WCOP RSBCK
W
WRTMASK
0x0009 FORBYP^{2 R}
0
0
0
0
W
0x000A CTCTL^{2 R}
0
0
0
0
W
R
0x000B ARMCOP
W
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
2. FORBYP and CTCTL are intended for factory test purposes only.
= Unimplemented or Reserved
3
2
1
SYNDIV[5:0]
REFDIV[5:0]
POSTDIV[4:0]
LOCK
ILAF
SCMIF
0
0
SCMIE
0
PLLWAI
RTIWAI
FSTWKP PRE
PCE
RTR3
0
0
RTR2
CR2
0
RTR1
CR1
0
0
0
0
0
Bit 3
0
Bit 2
0
Bit 1
Figure 11-2. CRG Register Summary
Bit 0
SCM
0
COPWAI
SCME
RTR0
CR0
0
0
0
Bit 0
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
MC9S12XE-Family Reference Manual Rev. 1.25
472
Freescale Semiconductor