S912XEG128J2MAA Datasheet, PDF (267/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.3.2.1 Interrupt Vector Base Register (IVBR)
Chapter 6 Interrupt (S12XINTV2)
Address: 0x0121
7
6
5
4
3
2
1
0
R
IVB_ADDR[7:0]
W
Reset
1
1
1
1
1
1
1
1
Figure 6-3. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Table 6-4. IVBR Field Descriptions
Field
Description
7–0
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
6.3.2.2 XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Address: 0x0126
7
6
5
4
3
2
1
0
R
0
0
0
0
0
W
XILVL[2:0]
Reset
0
0
0
0
0
0
0
1
= Unimplemented or Reserved
Figure 6-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime
Write: Anytime
Table 6-5. INT_XGPRIO Field Descriptions
Field
Description
2–0
XILVL[2:0]
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
accesses to this register will return all 0.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
267