S912XEG128J2MAA Datasheet, PDF (466/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 XGATE (S12XGATEV3)
START_XGATE
DUMMY_ISR
XGATE_DATA_FLASH
XGATE_DATA_SCI
XGATE_DATA_IDX
XGATE_DATA_MSG
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
CPX #XGATE_CODE_FLASH_END
BLS COPY_XGATE_CODE_LOOP
;###########################################
;#
START XGATE
#
;###########################################
MOVW #XGMCTL_ENABLE, XGMCTL
;enable XGATE
BRA *
;###########################################
;#
DUMMY INTERRUPT SERVICE ROUTINE
#
;###########################################
RTI
CPU XGATE
;###########################################
;#
XGATE DATA
#
;###########################################
ALIGN 1
EQU *
EQU *-XGATE_DATA_FLASH
DW SCI_REGS
;pointer to SCI register space
EQU *-XGATE_DATA_FLASH
DB XGATE_DATA_MSG
;string pointer
EQU *-XGATE_DATA_FLASH
FCC "Hello World!
;ASCII string
DB $0D
;CR
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END
XGATE_DUMMY_ISR_XG
;###########################################
;#
XGATE CODE
#
;###########################################
ALIGN 1
LDW R2,(R1,#XGATE_DATA_SCI)
;SCI -> R2
LDB R3,(R1,#XGATE_DATA_IDX)
;msg -> R3
LDB R4,(R1,R3+)
;curr. char -> R4
STB R3,(R1,#XGATE_DATA_IDX)
;R3 -> idx
LDB R0,(R2,#(SCISR1-SCI_REGS))
;initiate SCI transmit
STB R4,(R2,#(SCIDRL-SCI_REGS))
;initiate SCI transmit
CMPL R4,#$0D
BEQ XGATE_CODE_DONE
RTS
LDL R4,#$00
;disable SCI interrupts
STB R4,(R2,#(SCICR2-SCI_REGS))
LDL R3,#XGATE_DATA_MSG;reset R3
STB R3,(R1,#XGATE_DATA_IDX)
RTS
EQU (XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
10.9.3 Stack Support
To simplify the implementation of a program stack the XGATE can be configured to set RISC core register
R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined:
One for threads of priority level 7 to 4 (refer to Section 10.3.1.5, “XGATE Initial Stack Pointer for
MC9S12XE-Family Reference Manual Rev. 1.25
466
Freescale Semiconductor