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S912XEG128J2MAA Datasheet, PDF (28/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 1 Device Overview MC9S12XE-Family
⢠16-Bit CPU12X
â Upward compatible with MC9S12 instruction set with the exception of ï¬ve Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed
â Enhanced indexed addressing
â Access to large data segments independent of PPAGE
⢠INT (interrupt module)
â Eight levels of nested interrupts
â Flexible assignment of interrupt sources to each interrupt level.
â External non-maskable high priority interrupt (XIRQ)
â Internal non-maskable high priority Memory Protection Unit interrupt
â Up to 24 pins on ports J, H and P conï¬gurable as rising or falling edge sensitive interrupts
⢠EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)
â Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces
â Each chip select output can be conï¬gured to complete transaction on either the time-out of one
of the two wait state generators or the deassertion of EWAIT signal
⢠MMC (module mapping control)
⢠DBG (debug module)
â Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests
â 64 x 64-bit circular trace buffer captures change-of-ï¬ow or memory access information
⢠BDM (background debug mode)
⢠MPU (memory protection unit)
â 8 address regions deï¬nable per active program task
â Address range granularity as low as 8-bytes
â No write / No execute Protection Attributes
â Non-maskable interrupt on access violation
⢠XGATE
â Programmable, high performance I/O coprocessor module
â Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states
â Performs logical, shifts, arithmetic, and bit operations on data
â Can interrupt the HCS12X CPU signalling transfer completion
â Triggers from any hardware module as well as from the CPU possible
â Two interrupt levels to service high priority tasks
â Hardware support for stack pointer initialisation
⢠OSC_LCP (oscillator)
â Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
â Good noise immunity
â Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
â Transconductance sized for optimum start-up margin for typical crystals
⢠IPLL (Internally ï¬ltered, frequency modulated phase-locked-loop clock generation)
MC9S12XE-Family Reference Manual Rev. 1.25
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Freescale Semiconductor
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