S912XEG128J2MAA Datasheet, PDF (138/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-41. PTP Register Field Descriptions (continued)
Field
3
PTP
2
PTP
1
PTP
0
PTP
Description
Port P general purpose input/output data—Data Register
Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 2 is associated with the PWM output channel 2 and the SCK signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 2 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 1 is associated with the PWM output channel 1 and the MOSI signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 1 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Port P general purpose input/output data—Data Register
Port P pin 0 is associated with the PWM output channel 0 and the MISO signal of SPI1.
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 0 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.46 Port P Input Register (PTIP)
Address 0x0259
7
R PTIP7
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
W
Reset
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-44. Port P Input Register (PTIP)
1. Read: Anytime.
Write:Never, writes to this register have no effect.
Access: User read⁽¹⁾
1
PTIP1
0
PTIP0
u
u
MC9S12XE-Family Reference Manual Rev. 1.25
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