S912XEG128J2MAA Datasheet, PDF (584/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
SDA
SCL
SCL Hold(start)
SCL Hold(stop)
START condition
STOP condition
Figure 15-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 15-7. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
NOTE
A master SCL divider period can be prolonged at higher internal bus
frequencies. This happens when the internal bus cycle length becomes equal
to a pad delay. The SCL input is used for clock arbitration of multiple
masters. Thus after each SCL edge is internally driven an extra bus period
is counted before the pad level is attained, allowing the next toggle. This has
the effect of extending the SCL Divider values in Table 15-7 for MUL=1
and IBC[7:0] = 0x00 to 0x0F.
IBC[7:0]
(hex)
MUL=1
00
01
02
03
04
05
Table 15-7. IIC Divider and Hold Values (Sheet 1 of 6)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
20
7
6
22
7
7
24
8
8
26
8
9
28
9
10
30
9
11
SCL Hold
(stop)
11
12
13
14
15
16
MC9S12XE-Family Reference Manual Rev. 1.25
584
Freescale Semiconductor