S912XEG128J2MAA Datasheet, PDF (329/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 S12X Debug (S12XDBGV3) Module
NOTE
Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte
by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access
size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs
to comparator register contents or when the data bus is equivalent to the comparator register contents.
8.4.2.2 Exact Address Comparator Match (Comparators B and D)
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match
qualification functions the same as for comparators A and C.
If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the
specified type of access causes a match. Thus if configured for a byte access of a particular address, a word
access covering the same address does not lead to match.
Table 8-40. Comparator Access Size Considerations
Comparator
Comparators
A and C
Comparators
B and D
Comparators
B and D
Address
ADDR[n]
SZE SZ8
——
ADDR[n]
0
X
ADDR[n]
1
0
Condition For Valid Match
Word and byte accesses of ADDR[n]⁽¹⁾
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Word and byte accesses of ADDR[n]¹
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Word accesses of ADDR[n]¹
MOVW #$WORD ADDR[n]
Comparators
ADDR[n]
1
1
Byte accesses of ADDR[n]
B and D
MOVB #$BYTE ADDR[n]
1. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address used in the code.
8.4.2.3 Data Bus Comparison NDB Dependency
Comparators A and C each feature an NDB control bit, which allows data bus comparators to be configured
to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the
contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A
match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register
bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any
data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored
and prevents a match because no difference can be detected. In this case address bus equivalence does not
cause a match.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
329