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S912XEG128J2MAA Datasheet, PDF (682/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
18.3.0.3 PIT Channel Enable Register (PITCE)
Module Base + 0x0002
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
PCE3
PCE2
0
0
0
0
0
Figure 18-5. PIT Channel Enable Register (PITCE)
Read: Anytime
Write: Anytime
1
PCE1
0
0
PCE0
0
Table 18-4. PITCE Field Descriptions
Field
Description
3:0
PCE[3:0]
PIT Enable Bits for Timer Channel 3:0 â These bits enable the PIT channels 3-0. If PCE is cleared, the PIT
channel is disabled and the corresponding ï¬ag bit in the PITTF register is cleared. When PCE is set, and if the
PIT module is enabled (PITE = 1) the 16-bit timer counter is loaded with the start count value and starts down-
counting.
0 The corresponding PIT channel is disabled.
1 The corresponding PIT channel is enabled.
MC9S12XE-Family Reference Manual Rev. 1.25
682
Freescale Semiconductor
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