S912XEG128J2MAA Datasheet, PDF (243/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 External Bus Interface (S12XEBIV4)
Refer to the S12X_MMC section for a detailed description of the MCU operating modes.
5.1.4 Block Diagram
Figure 5-1 is a block diagram of the XEBI with all related I/O signals.
ADDR[22:0]
DATA[15:0]
IVD[15:0]
LSTRB
RW
EWAIT
XEBI
UDS
LDS
RE
WE
ACC[2:0]
IQSTAT[3:0]
CS[3:0]
Figure 5-1. XEBI Block Diagram
5.2 External Signal Description
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
NOTE
The following external bus related signals are described in other sections:
ECLK, ECLKX2 (free-running clocks) — PIM section
TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
Table 5-2 outlines the pin names and gives a brief description of their function. Refer to the SoC section
and PIM section for reset states of these pins and associated pull-ups or pull-downs.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
243