S912XEG128J2MAA Datasheet, PDF (527/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 14
Enhanced Capture Timer (ECT16B8CV3)
Table 14-1. Revision History
Revision
Number
Revision Date
Sections
Affected
Description of Changes
V03.06
V03.07
V03.08
05 Aug 2009
26 Aug 2009
04 May 2010
14.3.2.15/14-
549
14.3.2.16/14-
551
14.3.2.24/14-
557
14.3.2.29/14-
562
14.4.1.1.2/14-
573
update register PACTL bit4 PEDGE PT7 to IC7
update register PAFLG bit0 PAIF PT7 to IC7,update bit1 PAOVF PT3 to IC3
update register ICSYS bit3 TFMOD PTx to ICx
update register PBFLG bit1 PBOVF PT1 to IC1
update IC Queue Mode description.
14.3.2.2/14-536 - Add description, ?a counter overflow when TTOV[7] is set?, to be the
14.3.2.3/14-536 condition of channel 7 override event.
14.3.2.4/14-537 - Phrase the description of OC7M to make it more explicit
14.3.2.8/14-540 - Add Table 14-11
14.3.2.11/14- - TCRE description, add Note and Figure 14-17
543
14.1 Introduction
The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module
enhanced by additional features in order to enlarge the field of applications, in particular for automotive
ABS applications.
This design specification describes the standard timer as well as the additional features.
The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can
be used for many purposes, including input waveform measurements while simultaneously generating an
output waveform. Pulse widths can vary from microseconds to many seconds.
A full access for the counter registers or the input capture/output compare registers will take place in one
clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same
result as accessing them in one word.
14.1.1 Features
• 16-bit buffer register for four input capture (IC) channels.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
527