S912XEG128J2MAA Datasheet, PDF (166/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-84. RDRR Register Field Descriptions
Field
7-0
RDRR
Description
Port R reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
2.3.89 Port R Pull Device Enable Register (PERR)
Address 0x036C
R
W
Reset
7
PERR7
0
1. Read: Anytime.
Write: Anytime.
6
PERR6
5
PERR5
4
PERR4
3
PERR3
2
PERR2
Access: User read/write⁽¹⁾
1
0
PERR1
PERR0
0
0
0
0
0
0
0
Figure 2-87. Port R Pull Device Enable Register (PERR)
Table 2-85. PERR Register Field Descriptions
Field
7-0
PERR
Description
Port R pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.90 Port R Polarity Select Register (PPSR)
Address 0x036D
R
W
Reset
7
PPSR7
0
1. Read: Anytime.
Write: Anytime.
6
PPSR6
5
PPSR5
4
PPSR4
3
PPSR3
2
PPSR2
0
0
0
0
0
Figure 2-88. Port R Polarity Select Register (PPSR)
Access: User read/write⁽¹⁾
1
0
PPSR1
PPSR0
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
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