S912XEG128J2MAA Datasheet, PDF (148/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.59 Port H Interrupt Enable Register (PIEH)
Read: Anytime.
Address 0x0266
R
W
Reset
7
PIEH7
0
1. Read: Anytime.
Write: Anytime.
6
PIEH6
5
PIEH5
4
PIEH4
3
PIEH3
2
PIEH2
0
0
0
0
0
Figure 2-57. Port H Interrupt Enable Register (PIEH)
Access: User read/write⁽¹⁾
1
0
PIEH1
PIEH0
0
0
Field
7-0
PIEH
Table 2-55. PPSP Register Field Descriptions
Description
Port H interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.60 Port H Interrupt Flag Register (PIFH)
Address 0x0267
R
W
Reset
7
PIFH7
0
1. Read: Anytime.
Write: Anytime.
6
PIFH6
5
PIFH5
4
PIFH4
3
PIFH3
2
PIFH2
0
0
0
0
0
Figure 2-58. Port H Interrupt Flag Register (PIFH)
Access: User read/write⁽¹⁾
1
0
PIFH1
PIFH0
0
0
Field
7-0
PIFH
Table 2-56. PPSP Register Field Descriptions
Description
Port H interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSH register. To clear this flag, write logic level 1 to the corresponding bit in the PIFH register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
MC9S12XE-Family Reference Manual Rev. 1.25
148
Freescale Semiconductor