S912XEG128J2MAA Datasheet, PDF (248/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-7. EBICTL1 Field Descriptions
Field
Description
6–4
External Access Stretch Option 1 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
EXSTR1[2:0] stretch cycles on every access to the external address space as shown in Table 5-8.
2–0
External Access Stretch Option 0 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
EXSTR0[2:0] stretch cycles on every access to the external address space as shown in Table 5-8.
Table 5-8. External Access Stretch Bit Definition
EXSTRx[2:0]
000
001
010
011
100
101
110
111
Number of Stretch Cycles
1
2
3
4
5
6
7
8
5.4 Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
5.4.1 Operating Modes and External Bus Properties
A summary of the external bus interface functions for each operating mode is shown in Table 5-9.
Table 5-9. Summary of Functions
Properties
(if Enabled)
PRR access⁽¹⁾
Internal access
visible externally
External
address access
and
unimplemented area
access⁽²⁾
Single-Chip Modes
Normal
Special
Single-Chip Single-Chip
Normal
Expanded
2 cycles
read internal
write internal
—
Timing Properties
2 cycles
read internal
write internal
2 cycles
read internal
write internal
—
—
Expanded Modes
Emulation
Single-Chip
Emulation
Expanded
2 cycles
read external
write int & ext
1 cycle
2 cycles
read external
write int & ext
1 cycle
—
—
Max. of 2 to 9
1 cycle
Max. of 2 to 9
programmed
programmed
cycles
cycles
or n cycles of
ext. wait⁽³⁾
or n cycles of
ext. wait³
Special
Test
2 cycles
read internal
write internal
1 cycle
1 cycle
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