S912XEG128J2MAA Datasheet, PDF (154/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.67 Port J Interrupt Enable Register (PIEJ)
Read: Anytime.
Address 0x026E
R
W
Reset
7
PIEJ7
0
1. Read: Anytime.
Write: Anytime.
6
PIEJ6
5
PIEJ5
4
PIEJ4
3
PIEJ3
2
PIEJ2
0
0
0
0
0
Figure 2-65. Port J Interrupt Enable Register (PIEJ)
Access: User read/write⁽¹⁾
1
0
PIEJ1
PIEJ0
0
0
Field
7-0
PIEJ
Table 2-63. PPSP Register Field Descriptions
Description
Port J interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
2.3.68 Port J Interrupt Flag Register (PIFJ)
Address 0x026F
R
W
Reset
7
PIFJ7
0
1. Read: Anytime.
Write: Anytime.
6
PIFJ6
5
PIFJ5
4
PIFJ4
3
PIFJ3
2
PIFJ2
0
0
0
0
0
Figure 2-66. Port J Interrupt Flag Register (PIFJ)
Access: User read/write⁽¹⁾
1
0
PIFJ1
PIFJ0
0
0
Field
7-0
PIFJ
Table 2-64. PPSP Register Field Descriptions
Description
Port J interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSJ register. To clear this flag, write logic level 1 to the corresponding bit in the PIFJ register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
MC9S12XE-Family Reference Manual Rev. 1.25
154
Freescale Semiconductor