S912XEG128J2MAA Datasheet, PDF (159/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.76
Chapter 2 Port Integration Module (S12XEPIMV1)
Port AD0 Pull Up Enable Register 1 (PER1AD0)
Address 0x0277
Access: User read/write⁽¹⁾
7
R
PER1AD07
W
6
PER1AD06
5
PER1AD05
4
PER1AD04
3
PER1AD03
2
PER1AD02
1
PER1AD01
0
PER1AD00
Reset
0
0
0
0
0
0
0
0
1. Read: Anytime.
Write: Anytime.
Figure 2-74. Port AD0 Pull Up Enable Register 1 (PER1AD0)
Table 2-72. PER1AD0 Register Field Descriptions
Field
Description
7-0 Port AD0 pull device enable—Enable pull devices on input pins
PER1AD0 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.77 Port AD1 Data Register 0 (PT0AD1)
Address 0x0278
7
R
PT0AD17
W
Altern.
Function
AN15
Reset
0
1. Read: Anytime.
Write: Anytime.
6
PT0AD16
5
PT0AD15
4
PT0AD14
3
PT0AD13
2
PT0AD12
AN14
AN13
AN12
AN11
AN10
0
0
0
0
0
Figure 2-75. Port AD1 Data Register 0 (PT0AD1)
Access: User read/write⁽¹⁾
1
0
PT0AD11 PT0AD10
AN9
AN8
0
0
Table 2-73. PT0AD1 Register Field Descriptions
Field
Description
7-0
PT0AD1
Port AD1 general purpose input/output data—Data Register
This register is associated with ATD1 analog inputs AN[15:8] on PAD[31:24], respectively.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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