S912XEG128J2MAA Datasheet, PDF (80/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview MC9S12XE-Family
MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.4.4.2 User State
This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes
register while in Supervisor state. Restrictions apply for the execution of several CPU instructions in User
state and access to system resources is only allowed in if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.5 Security
The MCU security feature allows the protection of the on chip Flash and emulated EEPROM memory. For
a detailed description of the security features refer to the S12X9SEC description.
1.6 Resets and Interrupts
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1 Resets
Resets are explained in detail in the Clock Reset Generator (CRG) description.
Table 1-13. Reset Sources and Vector Locations
Vector Address
Reset Source
CCR
Mask
Local Enable
$FFFE
$FFFE
$FFFE
$FFFE
$FFFC
$FFFA
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock monitor reset
COP watchdog reset
None
None
None
None
None
None
None
None
None
None
PLLCTL (CME, SCME)
COP rate select
1.6.2 Vectors
Table 1-14 lists all interrupt sources and vectors in the default order of priority. The interrupt module
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module.
MC9S12XE-Family Reference Manual Rev. 1.25
80
Freescale Semiconductor