S912XEG128J2MAA Datasheet, PDF (617/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 16-9. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
0
0
1 Tq clock cycle⁽¹⁾
0
0
1
2 Tq clock cycles
:
:
:
:
1
1
0
7 Tq clock cycles
1
1
1
8 Tq clock cycles
1. This setting is not valid. Please refer to Table 16-37 for valid settings.
Table 16-10. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
1 Tq clock cycle⁽¹⁾
0
0
0
1
2 Tq clock cycles¹
0
0
1
0
3 Tq clock cycles¹
0
0
1
1
4 Tq clock cycles
:
:
:
:
:
1
1
1
0
15 Tq clock cycles
1
1
1
1
16 Tq clock cycles
1. This setting is not valid. Please refer to Table 16-37 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 16-9 and Table 16-10).
Eqn. 16-1
Bit Time= ⁽---P----r---e---f-s-C--c---A-a----Nl--e--C-r----L--v--K-a----l--u----e----⁾ • (1 + TimeSegment1 + TimeSegment2)
16.3.2.5 MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Module Base + 0x0004
R
W
Reset:
7
WUPIF
0
6
CSCIF
5
RSTAT1
4
RSTAT0
3
TSTAT1
2
TSTAT0
Access: User read/write⁽¹⁾
1
0
OVRIF
RXF
0
0
0
0
0
0
0
= Unimplemented
Figure 16-8. MSCAN Receiver Flag Register (CANRFLG)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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