S912XEG128J2MAA Datasheet, PDF (259/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 External Bus Interface (S12XEBIV4)
• ECLKX2 rising edges have the same timing as ECLK edges.
• The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing
for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
5.5.2.2 Example 2b: Emulation Expanded Mode
This mode is used for emulation systems in which the target application is operating in normal expanded
mode.
If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals
UDS, LDS, RE, and WE from the ADDR0, LSTRB, and RW signals.
Figure 5-6 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI
ADDR[22:0]/IVD[15:0]
DATA[15:0]
Emulator
EMULMEM
PRU
PRR
Ports
LSTRB
RW
UDS
LDS
RE
WE
ADDR[22:20]/ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
CS[3:0]
EWAIT
ECLK
ECLKX2
Figure 5-6. Application in Emulation Expanded Mode
The timings of accesses with 1 stretch cycle are shown in
• Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’
• Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’
The associated timing numbers are given in
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
259