S912XEG128J2MAA Datasheet, PDF (218/1324 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Memory Mapping Control (S12XMMCV4)
XGATE
XGATE
DBG
CPU
S12X0
BDM
S12X1
FLEXRAY
S12X2
MMC “Crossbar Switch”
XBUS3
XBUS1
XBUS0
XRAM
XBUS2
BDM
EBI
FLFATSMH
EEE
resources
XSRAM
IPBI
Figure 3-23. MMC Block Diagram
3.4.4.1 Master Bus Prioritization regarding access conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
• CPU always has priority over BDM and XGATE.
• XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
• XGATE has priority over BDM.
• BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the
later case the suspect master will be stalled after finishing the current operation and the BDM will
gain access to the bus.
• In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
3.5 Initialization/Application Information
3.5.1 CALL and RTC Instructions
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
MC9S12XE-Family Reference Manual Rev. 1.25
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